1. Field of the Invention
The invention relates to a method and an apparatus for testing DRAM memory chips in multichip memory modules.
2. Description of the Related Art
Multichip memory modules, which combine a DRAM memory chip (volatile memory) and a flash chip (nonvolatile memory) in one housing, are increasingly gaining market share for memory components for apparatuses for mobile applications, e.g., mobile telephones or notebooks. While the flash chip stores programs and data which have to be retained even when the operating voltage is switched off, the DRAM memory chip is used to ensure fast access to data and program parts in an operative operating mode of the application apparatus.
An emerging trend is production of the multichip memory modules in the context of so-called Known-Good-Die (KGD) business models. This means that it is ensured that the unpackaged memory chip satisfies the same quality standard as the packaged memory chip. In the context of the KGD business models, DRAM memory chips and flash chips that have been tested at the wafer level are packaged in a multichip memory module and supplied, if appropriate, after a short component test. The question of an expected early failure rate of the multichip memory modules arises in this case. Manufacturers of flash chips solve this problem partly by means of a pure thermal stress of the wafers without an additional electrical stress, as a result of which an early failure of the flash chips is accelerated.
A customary way of lowering the early failure rate of DRAM memory chips consists of a burn-in lasting a number of hours (e.g., 2 to 20 hours), the duration of the operation depending on the state of the technology, the memory size and the production quality sought. In this case, each individual DRAM memory chip is exposed to continuous electrical stress at an elevated temperature. A simulation of this method at the wafer level is associated with considerable costs and technical problems, such as, for example, the requirement for simultaneous contact-connection of all the chips on the wafer. It is generally the case, therefore, that, under certain circumstances, greatly shortened test times are employed and, as a result thereof, a relatively high early failure rate of the DRAM memory chips is accepted, in a disadvantageous manner.
Typical applications of DRAM memory chips relate for example to graphical applications of the apparatuses mentioned, such as, by way of example, an image memory for the display of the mobile telephone. In these applications, a few pixel defects do not result in critical impairment of the functionality of the application. However, DRAM memory chips are also used as buffer memories for program parts and data, in the case of which a failure of memory cells of the DRAM memory chips can have an extremely disadvantageous effect. As a result, a high early failure rate can considerably impair the reliability of the DRAM memory chips and thus represent a non-negligible disadvantage.
Consequently, the object of the present invention is to provide a method and an apparatus which can be used to increase the reliability of DRAM memory chips in multichip memory modules, particularly for multichip memory modules being incorporated in apparatuses for mobile applications.